Overview:

This document describes ValueRAM's 128M x 64-bit (1GB) DDR3-1333MHz CL9 SDRAM (Synchronous DRAM) memory module, based on eight 128M x 8-bit DDR3-1333MHz FBGA components. The SPD is programmed to JEDEC standard latency 1333MHz timing of 9-9-9 at 1.5V.

Features:

• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 5,6,7,8,9,10
• Posted CAS
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7(DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4
• which does not allow seamless read or write [either on the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE . 95°C
• Asynchronous Reset
• PCB : Height 1.180” (30.00mm), double sided component